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Features
* 16-channel GPS Correlator
- 8192 Search Bins with GPS Acquisition Accelerator - Accuracy: 2.5m CEP (Stand-Alone, S/A off) - Time to First Fix: 34s (Cold Start) - Acquisition Sensitivity: -140 dBm - Tracking Sensitivity: -150 dBm Utilizes the ARM7TDMI(R) ARM(R) Thumb(R) Processor Core - High-performance 32-bit RISC Architecture - High-density 16-bit Instruction Set - EmbeddedICETM (In-circuit Emulator) 128 Kbyte Internal RAM 384 Kbyte Internal ROM, Firmware Version V5.0 Position Technology Provided by u-blox 6-channel Peripheral Data Controller (PDC) 8-level Priority, Individually Maskable, Vectored Interrupt Controller - 2 External Interrupts 24 User-programmable I/O Lines 1 USB Device Port - Universal Serial Bus (USB) V2.0 Full-speed Device - Embedded USB V2.0 Full-speed Transceiver - Suspend/Resume Logic - Ping-pong Mode for Isochronous and Bulk Endpoints 2 USARTs - 2 Dedicated Peripheral Data Controller (PDC) Channels per USART Master/Slave SPI Interface - 2 Dedicated Peripheral Data Controller (PDC) Channels - 8-bit to 16-bit Programmable Data Length - 4 External Slave Chip Selects Programmable Watchdog Timer Advanced Power Management Controller (APMC) - Peripherals Can Be Deactivated Individually - Geared Master Clock to Reduce Power Consumption - Sleep State with Disabled Master Clock - Hibernate State with 32.768 kHz Master Clock Real Time Clock (RTC) 2.3V to 3.6V or 1.8V Core Supply Voltage Includes Power Supervisor 1.8V to 3.3V User-definable I/O Voltage for Several GPIOs with 5V Tolerance 4 Kbytes Battery Backup Memory 8 mm x 8 mm 56 Pin QFN56 Package RoHS-compliant, Green
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GPS Baseband Processor ATR0622P1 Automotive Summary
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NOTE: This is a summary document. The complete document is available. For more information, please contact your local Atmel sales office.
4973AS-GPS-12/07
1. Description
The GPS baseband processor ATR0622P1 includes a 16-channel GPS correlator and is based on the ARM7TDMI processor core. This processor has a high-performance 32-bit RISC architecture and very low power consumption. In addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applications. The ATR0622P1 has two USART and an USB device port. This port is compliant with the Universal Serial Bus (USB) V2.0 full-speed device specification. The ATR0622P1 includes full GPS firmware, licensed from u-blox AG, which performs the basic GPS operation, including tracking, acquisition, navigation and position data output. For normal PVT (Position/Velocity/Time) applications, there is no need for off-chip Flash memory or ROM. The firmware supports e.g. the NMEA(R) protocol (2.1 and 2.3), a binary protocol for PVT data, configuration and debugging, the RTCM protocol for DGPS, SBAS (WAAS, EGNOS and MSAS) and A-GPS (aiding) it is also possible to store the configuration settings in an optional external EEPROM. The ATR0622P1 is manufactured using Atmel(R)'s high-density CMOS technology. By combining the ARM7TDMI microcontroller core with on-chip SRAM, 16-channel GPS correlator, and a wide range of peripheral functions on a monolithic chip, the ATR0622P1 provides a highly flexible and cost-effective solution for GPS applications.
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ATR0622P1
4973AS-GPS-12/07
ATR0622P1
Figure 1-1. ATR0622P1 Block Diagram
GPS Accelerator GPS Correlators
XT_IN XT_OUT
Advanced Power Management Controller
SRAM
RTC
NSHDN NSLEEP
RF_ON CLK23
SIGLO0 SIGHI0
SMD Generator
P0/NANTSHORT P14/NAADET1 P25/NAADET0 P20/TIMEPULSE P29/GPSMODE12 P27/GPSMODE11 P26/GPSMODE10 P24/GPSMODE8 P23/GPSMODE7 P19/GPSMODE6 P17/GPSMODE5 P13/GPSMODE3 P12/GPSMODE2 P1/GPSMODE0 P9/EXTINT0 P2/BOOT_MODE P30/AGCOUT0 P8/STATUSLED
PIO2 Controller
APB
SPI
Timer Counter
P15/ANTON
USART2
Special Function
P21/TXD2 PIO2 P22/RXD2
PIO2
Advanced Interrupt Controller
USART1
P18/TXD1 P31/RXD1
USB Transceiver
Watchdog
P16/NEEPROM
USB_DP USB_DM
B R I D G E
USB
ASB
Interface to Off-Chip Memory (EBI)
ARM7TDMI
Embedded ICE
DBG_EN NTRST TDI TDO TCK TMS JTAG
SRAM 128K
ROM 384K
PDC2
Reset Controller
Power Supply Manager
VBAT18 VBAT LDOBAT_IN LDO_OUT LDO_IN LDO_EN
NRESET
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4973AS-GPS-12/07
2. Architectural Overview
2.1 Description
The ATR0622P1 architecture consists of two main buses, the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB). The ASB is designed for maximum performance. It interfaces the processor with the on-chip 32-bit memories. The APB is designed for accesses to on-chip peripherals and is optimized for low power consumption. The AMBATM Bridge provides an interface between the ASB and the APB. An on-chip Peripheral Data Controller (PDC2) transfers data between the on-chip USARTs/SPI and the on-chip and off-chip memories without processor intervention. Most importantly, the PDC2 removes the processor interrupt handling overhead and significantly reduces the number of clock cycles required for a data transfer. It can transfer up to 64K contiguous bytes without reprogramming the starting address. As a result, the performance of the microcontroller is increased and the power consumption reduced. The ATR0622P1 peripherals are designed to be easily programmable with a minimum number of instructions. Each peripheral has a 16 Kbyte address space allocated in the upper 3 Mbyte of the 4 Gbyte address space. (Except for the interrupt controller, which has 4 Kbyte address space.) The peripheral base address is the lowest address of its memory space. The peripheral register set is composed of control, mode, data, status, and interrupt registers. To maximize the efficiency of bit manipulation, frequently written registers are mapped into three memory locations. The first address is used to set the individual register bits, the second resets the bits, and the third address reads the value stored in the register. A bit can be set or reset by writing a "1" to the corresponding position at the appropriate address. Writing a "0" has no effect. Individual bits can thus be modified without having to use costly read-modify-write and complex bit-manipulation instructions. All of the external signals of the on-chip peripherals are under the control of the Parallel I/O (PIO2) Controller. The PIO2 Controller can be programmed to insert an input filter on each pin or generate an interrupt on a signal change. After reset, the user must carefully program the PIO2 Controller in order to define which peripheral signals are connected with off-chip logic. The ARM7TDMI processor operates in little-endian mode on the ATR0622P1 GPS Baseband. The processor's internal architecture and the ARM and Thumb instruction sets are described in the ARM7TDMI datasheet. The ARM standard In-Circuit Emulator (ICE) debug interface is supported via the JTAG/ICE port of the ATR0622P1. For features of the ROM firmware, refer to the software documentation available from u-blox AG, Switzerland.
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ATR0622P1
4973AS-GPS-12/07
ATR0622P1
3. Pin Configuration
3.1 Pinout
Pinout QFN56 (Top View)
42 43 29 28
Figure 3-1.
ATR0622P1
56 1 14 15
Table 3-1.
Pin Name CLK23 DBG_EN GND LDOBAT_IN LDO_EN LDO_IN LDO_OUT NRESET NSHDN NSLEEP NTRST P0 P1 P2 P8 P9 P12 P13 Notes:
ATR0622P1 Pinout
QFN56 37 8
(2)
Pin Type IN IN IN IN IN IN OUT I/O OUT OUT IN I/O I/O I/O I/O I/O I/O I/O
Pull Resistor (Reset Value)(1) PD
PIO Bank A Firmware Label I O
21 25 20 19 41 26 24 13 40 47 46 48 29 49 32
Open drain PU
PD PD Configurable (PD) Configurable (PD) Configurable (PD) PU to VBAT18 Configurable (PU) PU to VBAT18 NANTSHORT GPSMODE0 BOOT_MODE STATUSLED EXTINT0 GPSMODE2 GPSMODE3 EXTINT1 EXTINT0 NPCS2 AGCOUT1 "0" "0"
1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset 2. Ground plane 3. VBAT18 represent the internal power supply of the backup power domain. 4. VDDIO is the supply voltage for the following GPIO-pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24, P25, P26, P27 and P29. 5. VDD_USB is the supply voltage for following the USB-pins: USB_DM and USB_DP. For operation of the USB interface, supply of 3.0V to 3.6V is required. 6. This pin is not connected
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4973AS-GPS-12/07
Table 3-1.
Pin Name P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P29 P30 P31 RF_ON SIGHI0 SIGLO0 TCK TDI TDO TMS USB_DM USB_DP VBAT VBAT18(3) VDD18 VDD18 VDD18 VDDIO(4) VDD_USB XT_IN XT_OUT NC(6) Notes:
(5)
ATR0622P1 Pinout (Continued)
QFN56 1 17 6 2 45 53 4 52 30 3 5 55 44 54 50 16 31 15 38 39 9 10 11 12 34 35 22 23 7, 14 18, 36 51 43, 56 33 28 27 42 Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O OUT IN IN IN IN OUT IN I/O I/O IN OUT IN IN IN IN IN IN OUT PU PU PU Pull Resistor (Reset Value)(1) Configurable (PD) PD Configurable (PU) Configurable (PD) Configurable (PU) Configurable (PU) Configurable (PD) Configurable (PU) PU to VBAT18 Configurable (PU) Configurable (PU) Configurable (PD) Configurable (PU) Configurable (PU) Configurable (PU) PD PU to VBAT18 PD PIO Bank A Firmware Label NAADET1 ANTON NEEPROM GPSMODE5 TXD1 GPSMODE6 TIMEPULSE TXD2 RXD2 GPSMODE7 GPSMODE8 NAADET0 GPSMODE10 GPSMODE11 GPSMODE12 AGCOUT0 RXD1 RXD1 RXD2 SCK MOSI MISO NSS SCK MOSI MISO NPCS0 NPCS1 NPCS3 AGCOUT0 SIGLO1 SCK2 SCK2 TXD2 SIGHI1 SCK1 SCK1 TXD1 I O "0"
1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset 2. Ground plane 3. VBAT18 represent the internal power supply of the backup power domain. 4. VDDIO is the supply voltage for the following GPIO-pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24, P25, P26, P27 and P29. 5. VDD_USB is the supply voltage for following the USB-pins: USB_DM and USB_DP. For operation of the USB interface, supply of 3.0V to 3.6V is required. 6. This pin is not connected
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ATR0622P1
4973AS-GPS-12/07
ATR0622P1
3.2 Signal Description
ATR0622P1 Signal Description
Name BOOT_MODE TXD1 to TXD2 USART RXD1 to RXD2 SCK1 to SCK2 USB APMC AIC USB_DP USB_DM RF_ON EXTINT0-1 External interrupt request Function Boot mode input Transmit data output Receive data input External synchronous serial clock USB data (D+) USB data (D-) Type Input Output Input I/O I/O I/O Output Input Active Level Comment - - - - - - - High/ Low/ Edge - Low Low - - - - - Low Low - - - - - - - - Low - Low Low Interface to ATR0601 PIO-controlled after reset Interface to ATR0601 PIO-controlled after reset Interface to ATR0601 Connect to pin LDO_EN RTC oscillator RTC oscillator PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset Input after reset Interface to ATR0601 Interface to ATR0601 PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset, internal pull-down resistor PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset
Table 3-2.
Module EBI
AGC
AGCOUT0-1 NSLEEP
Automatic gain control Sleep output Shutdown output Oscillator input Oscillator output SPI clock Master out slave in Master in slave out Slave select Slave select Programmable I/O port Digital IF Digital IF Digital IF Digital IF GPS synchronized time pulse GPS mode Status LED Enable EEPROM support Active antenna power on output Active antenna short circuit detection input Active antenna detection input
Output Output Output Input Output I/O I/O I/O I/O Output I/O Input Input Input Input Output Input Output Input Output Input Input
RTC
NSHDN XT_IN XT_OUT SCK MOSI
SPI
MISO NSS/NPCS0 NPCS1 to NPCS3
PIO
P0 to P31 SIGHI0 SIGLO0
GPS
SIGHI1 SIGLO1 TIMEPULSE GPSMODE0-12 STATUSLED NEEPROM
CONFIG
ANTON NANTSHORT NAADET0-1
Note:
1. The USB transceiver is disabled if VDD_USB < 2.0V. In this case the pins USB_DM and USB_DP are connected to GND (internal pull-down resistors). The USB transceiver is enabled if VDD_USB is within 3.0V and 3.6V.
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4973AS-GPS-12/07
Table 3-2.
Module
ATR0622P1 Signal Description (Continued)
Name TMS TDI TDO TCK NTRST DBG_EN Function Test mode select Test data in Test data out Test clock Test reset input Debug enable Clock input Reset input Type Input Input Output Input Input Input Input I/O Power Power Power Power Power Power Out LDO in LDO out LDO enable Power Power Input Active Level Comment - - - - Low High - Low - - - - - - - - - - Internal pull-up resistor Internal pull-down resistor Internal pull-down resistor Interface to ATR0601, Schmitt trigger input Open drain with internal pull-up resistor Core voltage 1.8V Variable IO voltage 1.65V to 3.6V USB voltage 0 to 2.0V or 3.0V to 3.6V(1) Ground 2.3V to 3.6V 1.5V to 3.6V 1.8V backup voltage 2.3V to 3.6V 1.8V core voltage, max. 80 mA Internal pull-up resistor Internal pull-up resistor
JTAG/ICE
CLOCK RESET
CLK23 NRESET VDD18 VDDIO
POWER
VDD_USB GND LDOBAT_IN
LDOBAT
VBAT VBAT18 LDO_IN
LDO18 Note:
LDO_OUT LDO_EN
1. The USB transceiver is disabled if VDD_USB < 2.0V. In this case the pins USB_DM and USB_DP are connected to GND (internal pull-down resistors). The USB transceiver is enabled if VDD_USB is within 3.0V and 3.6V.
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ATR0622P1
4973AS-GPS-12/07
ATR0622P1
3.3 External Connections for a Working GPS System
Example of an External Connection
SIGH SIGL SC PURF PUXTO NC SIGHI SIGLO CLK23 RF_ON NSLEEP NRESET
Figure 3-2.
ATR0601
ATR0622P1
P8 P20 USB_DM USB_DP
STATUS LED TIMEPULSE Optional USB Optional USART 1 Optional USART 2
see Table 3-15 see Table 3-15 see Table 3-15 see Table 3-15 see Table 3-15 see Table 3-15 NC NC NC NC NC NC GND +3V (see Power Supply)
P0 - 2 P9 P12 - 17 P19 P23 - 27 P29 - 30 TMS TCK TDI NTRST TDO DBG_EN GND NSHDN LDO_EN LDO_OUT VDD18 LDO_IN LDOBAT_IN VBAT18 VBAT
P31 P18 P22 P21
XT_IN XT_OUT 32.368 kHz (see RTC)
+3V (see Power Supply)
VDDIO
+3V (see Power Supply)
VDD_USB
+3V (see Power Supply) GND
NC: Not connected
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4973AS-GPS-12/07
4. Ordering Information
Extended Type Number ATR0622P1-PYQW ATR0622-EK1 ATR0622-DK1 Package QFN56 MPQ 2000 1 1 Remarks 8 mm x 8 mm, 0.50 mm pitch, ROM5, RoHS-compliant, green, automotive type Evaluation kit/Road test kit Development kit including example design information
5. Package QFN56
Package: QFN56 8 x 8 Exposed pad 6.5 x 6.5 Dimensions in mm Not indicated tolerances 0.05 56 1 42 0.9 max. 0.05-0.05 43
+0
8 6.5 56 1 Pin 1 ID
technical drawings according to DIN specifications
14 0.25 0.40.1
29 28 0.5 nom. 15
14
Drawing-No.: 6.543-5121.01-4 Issue: 1; 02.09.05
Moisture sensitivity level (MSL) = 3
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ATR0622P1
4973AS-GPS-12/07
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4973AS-GPS-12/07

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